Nanostructure with various widths

ABSTRACT

A semiconductor structures and a method for forming the same are provided. The semiconductor structure includes first silicon-containing layers, second silicon-containing layers, third silicon-containing layers, and fourth silicon-containing layers vertically suspended over a substrate and laterally spaced apart from each other. In addition, the first silicon-containing layers and the second silicon-containing layers are narrower than the third silicon-containing layers and the fourth silicon-containing layers. The semiconductor structure further includes first source/drain features, second source/drain features, third source/drain features, and fourth source/drain features attaching to opposite sides of the first silicon-containing layers, the second silicon-containing layers, the third silicon-containing layers, and the fourth silicon-containing layers, respectively. In addition, the first source/drain features are merged with the second source/drain features while the third source/drain features are spaced apart from the fourth source/drain features.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Divisional application of U.S. patent application Ser. No. 16/911,665, filed on Jun. 25, 2020, which is a Continuation-in-part application of U.S. patent application Ser. No. 16/103,704, filed on Aug. 14, 2018 (now U.S. Pat. No. 10,720,503 issued on Jul. 21, 2020), the entirety of which are incorporated by reference herein.

BACKGROUND

The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.

Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the gate-all around transistor (GAA). The GAA device gets its name from the gate structure which can extend around the channel region providing access to the channel on two or four sides.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1, 2A to 8A, 2B to 8B, 10A to 12A, and 10B to 12B are perspective views of a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.

FIG. 9 is a cross-sectional view taken along a cross-sectional line of FIG. 8A or

FIG. 8B.

FIG. 13A is a cross-sectional view taken along a cross-sectional line of FIG. 12A.

FIG. 13B is a cross-sectional view taken along a cross-sectional line of FIG. 12B.

FIGS. 14A-1, 14B-1, 14C-1, 14D-1, 14E-1, 14F-1, 14G-1, 14H-1, 14I-1, 14J-1 , and 14K-1 are perspective views of a method for manufacturing a first device region in a semiconductor structure at various stages in accordance with some embodiments.

FIGS. 14A-2, 14B-2, 14C-2, 14D-2, 14E-2, 14F-2, 14G-2, 14H-2, 14I-2, 14J-2 , and 14K-2 are perspective views of a method for manufacturing a second device region in the semiconductor structure at various stages in accordance with some embodiments.

FIG. 15-1 illustrates a cross-sectional view of the semiconductor structure taken along a cross-sectional line A-A₁ shown in FIG. 14K-1 in accordance with some embodiments.

FIG. 15-2 illustrates a cross-sectional view of the semiconductor structure taken along a cross-sectional line A′-A₁′ shown in FIG. 14K-2 in accordance with some embodiments.

FIG. 16-1 illustrates a cross-sectional view of the semiconductor structure taken along a cross-sectional line B-B₁ shown in FIG. 14K-1 in accordance with some embodiments.

FIG. 16-2 illustrates a cross-sectional view of the semiconductor structure taken along a cross-sectional line B′-B₁′ shown in FIG. 14K-2 in accordance with some embodiments.

FIG. 17-1 illustrates a cross-sectional view of the semiconductor structure taken along a cross-sectional line C-C₁ shown in FIG. 14K-1 in accordance with some embodiments.

FIG. 17-2 illustrates a cross-sectional of the semiconductor structure view taken along a cross-sectional line C′-C₁′ shown in FIG. 14K-2 in accordance with some embodiments.

FIG. 18-1 illustrates a layout of the first device region of the semiconductor structures in accordance with some embodiments.

FIG. 18-2 illustrates a layout of the second device region of the semiconductor structures in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Gate all around (GAA) transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

FIGS. 1-8B and 10A-12B are perspective views of a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure. FIG. 9 is a cross-sectional view taken along a cross-sectional line of FIG. 8A or FIG. 8B. FIG. 13A is a cross-sectional view taken along a cross-sectional line of FIG. 12A. FIG. 13B is a cross-sectional view taken along a cross-sectional line of FIG. 12B.

Reference is made to FIGS. 1, 2A and 2B. The semiconductor device 10 includes a substrate 100 and device features can be formed on, above or over the substrate 100. The fin activation area 10 a is referred as a fin activation area with plural fins, e.g., in SRAM, random logic or input/output area, and the first fin activation area 10 b is referred as a fin activation area with a single fin, e.g., stand cell.

The substrate 100 may be a bulk silicon substrate. Alternatively, the substrate 100 may include an elementary semiconductor, such as silicon (Si) or germanium (Ge) in a crystalline structure; a compound semiconductor, such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); or combinations thereof. Possible substrates 100 also include a silicon-on-insulator (SOI) substrate. SOI substrates are fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods.

The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; or combinations thereof. The doped regions may be formed directly on the substrate 100, in a P-well structure, in an N-well structure, in a dual-well structure, and/or using a raised structure. The substrate 100 may further include various active regions, such as regions configured for an N-type metal-oxide-semiconductor transistor device and regions configured for a P-type metal-oxide-semiconductor transistor device.

A series of nano epitaxy layers 104 and sacrificial nano epitaxy layers 102 are alternately epitaxially grown on the substrate 100 for fin structure to form a nano epitaxy layer stack. In some embodiments, the nano epitaxy layer 104 may be nano epitaxy Silicon (Si) layer, and the present disclosure is not limited in this respect. In some embodiments, the sacrificial nano epitaxy layer 102 may be a nano epitaxy Silicon (Si)-Germanium (Ge) layer, and the present disclosure is not limited in this respect.

In some embodiments, the nano epitaxy layer 104 may have a thickness ranging from about 3 nm to about 7 nm, and the present disclosure is not limited in this respect. In some embodiments, the sacrificial nano epitaxy layer 102 may have a thickness ranging from about 2 nm to about 10 nm, and the present disclosure is not limited in this respect.

In some embodiments, a pad oxide layer 106, a pad nitride layer 108 and a mask layer 110 are deposited over the alternately-formed nano epitaxy layers 104 and sacrificial nano epitaxy layers 102. In some embodiments, the pad oxide layer 106 may be a thin film including silicon oxide formed, for example, using a thermal oxidation process. The pad oxide layer 106 may act as an adhesion layer between the nano epitaxy layers (102, 104) and the pad nitride layer 108. In some embodiments, the pad nitride layer 108 may be formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). In some embodiments, the mask layer 110 may be formed of thick silicon oxide for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The mask layer 110 is used as a hard mask during following processes, such as photolithography.

Reference is made to FIGS. 2A and 2B again. The pad oxide layer 106, the pad nitride layer 108 and the mask layer 110 are patterned to form mask structures with uniform widths both in the fin activation area 10 a and in the fin activation area 10 b, e.g., each combination of the pad oxide layer 106 a, the pad nitride layer 108 a and the mask layer 110 a in the fin activation area 10 a has a uniform width that is substantially equal to that of the combination of the pad oxide layer 106 b, the pad nitride layer 108 b and the mask layer 110 b in the fin activation area 10 b.

Reference is made to FIGS. 3A and 3B. A spacer cap layer 112 is conformally formed over the patterned pad oxide layer 106 a, pad nitride layer 108 a and mask layer 110 a in the fin activation area 10 a and over the patterned pad oxide layer 106 b, pad nitride layer 108 b and mask layer 110 b in the fin activation area 10 b.

In some embodiments, the spacer cap layer 112 may be formed of thin silicon oxide for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

Reference is made to FIGS. 4A and 4B. A photo resist layer 113 is deposited over the fin activation area 10 b as a mask structure and an etching process is performed both on the fin activation area 10 a and in the fin activation area 10 b. After the etching process, the spacer cap layer 112 in the fin activation area 10 a is removed while the spacer cap layer 112 in the fin activation area 10 b is protected by the photo resist layer 113 and not removed. In some embodiments, the photo resist layer 113 and the remained spacer cap layer 112 may have substantially the same width in the fin activation area 10 b.

In some embodiments, the photo resist layer 113 may be removed before fin etching processes. In some embodiments, a portion of the remained spacer cap layer 112 in contact with the top sacrificial nano epitaxy layer 102 may be removed by a selective etching (i.e., etch the remained spacer cap layer 112 in the fin activation area 10 b and not etch the top sacrificial nano epitaxy layer 102 in the fin activation area 10 a) before fin etching processes such that the spacer cap layer 112 is remained merely upon sidewalls of the patterned pad oxide layer 106, pad nitride layer 108 and mask layer 110 as part of the mask structure when fin etching processes are performed.

Reference is made to FIGS. 5A and 5B. One or more etching process(es) are performed to form multiple fin structures 105 a in a lengthwise direction 130 in the fin activation area 10 a and single fin structure 105 b in a lengthwise direction 130 in the fin activation area 10 b. Each fin structure 105 a includes a base fin 101 a protruding from the semiconductor substrate 100 a and multiple patterned nano epitaxy layers 104 a and sacrificial nano epitaxy layers 102 a stacked above the base fin 101 a. Each fin structure 105 b includes a base fin 101 b protruding from the semiconductor substrate 100 a and multiple alternate nano epitaxy layers 104 b and sacrificial nano epitaxy layers 102 b stacked above the base fin 101 b.

In some embodiments, the fin structures 105 a may be etched by capping the patterned pad oxide layer 106, pad nitride layer 108 and mask layer 110 on top of the fin structures 105 a in the fin activation area 10 a. And, the fin structure 105 b may be etched by capping the patterned pad oxide layer 106, pad nitride layer 108, and mask layer 110 as well as the remained spacer cap layer 112 on top of the fin structures 105 b in the fin activation area 10 b. The remained spacer cap layer 112 is located on used to broaden a width of the mask layer in order to obtain the relatively wide fin structure 105 b during the fin patterning process.

After fin patterning process, the fin structures 105 a are formed under the patterned pad oxide layer 106, pad nitride layer 108 and mask layer 110 in the fin activation area 10 a while the fin structure 105 b is formed under the patterned pad oxide layer 106, pad nitride layer 108, and mask layer 110 as well as the remained spacer cap layer 112 in the fin activation area 10 b.

In some embodiments, the etching process may include dry etching process, wet etching process, and/or combination thereof. The recessing process may also include a selective wet etch or a selective dry etch. A wet etching solution includes a tetramethylammonium hydroxide (TMAH), a HF/HNO3/CH3COOH solution, or other suitable solution. The dry and wet etching processes have etching parameters that can be tuned, such as etchants used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and other suitable parameters. For example, a wet etching solution may include NH4OH, KOH (potassium hydroxide), HF (hydrofluoric acid), TMAH (tetramethylammonium hydroxide), other suitable wet etching solutions, or combinations thereof. Dry etching processes include a biased plasma etching process that uses a chlorine-based chemistry. Other dry etchant gasses include CF4, NF3, SF6, and He. Dry etching may also be performed anisotropically using such mechanisms as DRIE (deep reactive-ion etching).

Fin structures are formed over the substrate 100 a within different functional regions, e.g., a LOGIC region and/or a memory region. In some embodiments, the fin structures may be of the same type or of different types. For example, some of the fin structures are n-type semiconductor fins, and the others of the fin structures are p-type semiconductor fins, and the present disclosure is not limited in this respect.

In some embodiments, each fin structure 105 a in the fin activation area 10 a is formed with a uniform width (W1) that is substantially equal to a uniform width (W1) of the other fin structure 105 a in the fin activation area 10 a. In some embodiments, the single fin structure 105 b in the fin activation area 10 b is formed with a uniform width (W2) that is greater than that (W1) of the fin structure 105 a in the fin activation area 10 a. The uniform width (W1) and width (W2) are measured in a direction that is perpendicular to the lengthwise direction 130.

Reference is made to FIGS. 6A and 6B. One or more etching process(es) are performed to remove the pad oxide layer 106 and pad nitride layer 108 on the fin structure 105 a in the fin activation area 10 a and to remove the remained pad oxide layer 106 b, pad nitride layer 108 b and the spacer cap layer 112 b on the fin structure 105 b in the fin activation area 10 b.

A field oxide layer 114 is formed to fill into trenches both in the fin activation area 10 a and the fin activation area 10 b to form a shallow trench isolation (STI). In some embodiments, at least the base fin 101 a of each fin structure 105 a is embedded within the field oxide layer 114 and at least the base fin 101 b of each fin structure 105 b is embedded within the field oxide layer 114.

In some embodiments, at least the multiple alternate nano epitaxy layers 104 a and sacrificial nano epitaxy layers 102 a of each fin structure 105 a may be located above the STI (i.e., the field oxide layer 114) and at least the multiple alternate nano epitaxy layers 104 b and sacrificial nano epitaxy layers 102 b of each fin structure 105 b may be located above the STI (i.e., the field oxide layer 114).

Reference is made to FIGS. 7A and 7B. A thin oxide layer 155 is formed over the STI (i.e., the field oxide layer 114) and the fin structures 105 a and 105 b. The oxide layer 155 may act as gate dielectric in later process. Plural dummy gates are formed over the oxide layer 155, in which the dummy gate 180 a crosses the plural fin structures 105 a in a direction 140, and the dummy gate 180 b crosses the single fin structures 105 b in a direction 140. In some embodiments, the direction 140 may be perpendicular to the lengthwise direction 130.

In some embodiments, mask layers 182 and 184 are formed over the dummy gates 180 a and 180 b. The mask layers 182 and 184 acts as a hard mask during the patterning process of the dummy gates 180 a and 180 b and may act as a hard mask during the following processes, such as etching. In some embodiments, the mask layers 182 and 184 may include silicon oxide, silicon nitride and/or silicon oxynitride.

In some embodiments, the dummy gates 180 a and 180 b may include polycrystalline-silicon (poly-Si) or poly-crystalline silicon-germanium (poly-SiGe). Further, the dummy gates may be doped poly-silicon with uniform or non-uniform doping. In some embodiments, the dummy gates 180 a and 180 b may be formed by, for example, forming a dummy gate material layer over the oxide layer 155. Patterned masks, such as mask layers 182 and 184, are formed over the dummy gate material layer. Then, the dummy gate material layer may be patterned using one or more etching processes, such as one or more dry plasma etching processes or one or more wet etching processes. During the etching process, the patterned mask may act as an etching mask. At least one parameter, such as etchant, etching temperature, etching solution concentration, etching pressure, source power, radio frequency (RF) bias voltage, etchant flow rate, of the patterning (or etching) recipe can be tuned. For example, dry etching process, such as plasma etching, may be used to etch the dummy gate material layer and the oxide layer 155 until the fin structures 105 a and 105 b are exposed.

Reference is made to FIGS. 8A and 8B. Gate spacer structures including plural gate spacers 190 on opposite sidewalls of the dummy gates 180 a and 180 b are formed. In some embodiments, at least one of the gate spacers 190 includes single or multiple layers. The gate spacers 190 can be formed by blanket depositing one or more dielectric layer(s) on the previously formed structure. The dielectric layer(s) may include silicon nitride (SiN), oxynitride, silicion carbon (SiC), silicon oxynitride (SiON), oxide, and the like. The gate spacers 190 may be formed by methods such as CVD, plasma enhanced CVD, sputter, or the like. The gate spacers 190 may then be patterned, such as by one or more etch processes to remove horizontal portions of the gate spacers 190 from the horizontal surfaces of the structure.

The oxide layer 155 exposed from the dummy gates 180 a and 180 b and the gate spacers 190 are removed by suitable process, such as etching. The remained portions of the oxide layer 155 are disposed under the dummy gates 180 a and 180 b and the gate spacers 190. Thus, the remained portions of the oxide layer 155 may be referred to as gate dielectric. Also, the dummy gate 180 a and 180 b and the remained oxide layer 155 may collectively be referred to as a dummy gate structure.

In some embodiments, the fin structures 105 a exposed from the dummy gates 180 a and the gate spacers 190 are removed by suitable process, such as etching, while the fin structures 105 b exposed from the dummy gates 180 b and the gate spacers 190 are removed by suitable process, such as etching.

Plural source/drain features 200 are respectively formed over the exposed base fins 101 a and 101 b of the substrate 100. In some embodiments, the wider source/drain features 200 are respectively formed over the exposed base fins 101 a, in which each base fin 101 a is equipped with a relatively narrow width, i.e., compared with the base fin 101 b. In some embodiments, the thinner source/drain features 200 are respectively formed over the exposed base fin 101 b that is equipped with a relatively large width, i.e., compared with the base fin 101 a.

In some embodiments, the source/drain features 200 may be epitaxy structures, and may also be referred to as epitaxy features 200. The source/drain features 200 may be formed using one or more epitaxy or epitaxial (epi) processes, such that Si features, SiGe features, and/or other suitable features can be formed in a crystalline state on the semiconductor base fins 101 a and 101 b. In some embodiments, the source/drain features 200 may be cladding over the semiconductor base fins 101 a and 101 b.

In some embodiments, lattice constants of the source/drain features 200 are different from lattice constants of the semiconductor base fins 101 a and 101 b, such that channels in the semiconductor base fins 101 a and 101 b are strained or stressed to enable carrier mobility of the semiconductor device and enhance the device performance. In some embodiments, the source/drain features 200 may include semiconductor material such as germanium (Ge) or silicon (Si); or compound semiconductor materials, such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), silicon germanium (SiGe), silicon carbide (SiC), or gallium arsenide phosphide (GaAsP).

The epitaxy processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxy process may use gaseous and/or liquid precursors, which interact with the composition of the semiconductor fins 110 (e.g., silicon). The source/drain features 200 may be in-situ doped. The doping species include P-type dopants, such as boron or BF2; N-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the source/drain features 200 are not in-situ doped, a second implantation process (i.e., a junction implant process) is performed to dope the source/drain features 200. One or more annealing processes may be performed to activate the source/drain features 200. The annealing processes include rapid thermal annealing (RTA) and/or laser annealing processes.

In some embodiments, the source/drain features 200 over the semiconductor base fins 101 a and 101 b may include the same doping-type, and the source/drain feature 200 over one of the semiconductor base fins 101 a and 101 b may include different doping-types. For example, some source/drain features 200 may be n-type, and the other source/drain features 200 may be p-type, and vise versa.

Reference is made to FIG. 9 , which is a cross-sectional view taken along a cross-sectional line of FIG. 8A or FIG. 8B. In some embodiments, an inner spacer layer 192 is formed between the source/drain features 200 and the sacrificial nano epitaxy layers 102 a/102 b. The inner spacer layer 192 may be formed after removing the fin structures 105 a exposed from the dummy gates 180 a and the gate spacers 190. The inner spacer layer 192 may be formed of dielectric materials by methods such as CVD, plasma enhanced CVD, sputter, or the like. The nano epitaxy layers 104 a/104 b interconnects the source/drain features 200.

Reference is made to FIGS. 10A and 10B. An etching stop layer 215 and interlayer dielectric 220 is formed over the source/drain features 200. Then, a CMP process is performed to remove the excessive interlayer dielectric 220, and the mask layers 182 and 184 (referring to FIGS. 11A and 11B) until the dummy gates 180 a and 180 b are exposed.

In some embodiments, the interlayer dielectric 220 may include silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbide, silicon germanium, or combinations thereof. The interlayer dielectric 220 may be formed by a suitable technique, such as CVD, ALD and spin-on coating. In some embodiments, air gaps may be created in the interlayer dielectric 220.

Then, a replacement gate (RPG) process scheme is employed. The dummy gates 180 a and 180 b are replaced with metal gates. For example, the dummy gates 180 a and 180 b are removed to from a plurality of gate trenches and expose the multiple alternate nano epitaxy layers and sacrificial nano epitaxy layers. The dummy gate gates 180 a and 180 b are removed by a selective etch process, including a selective wet etch or a selective dry etch, and carries a substantially vertical profile of the gate spacers 190.

Reference is made to FIGS. 11A and 11B. The sacrificial nano epitaxy layers 102 a/102 b are removed by a selective etch process, including a selective wet etch or a selective dry etch, and the remained nano epitaxy layers 104 a/104 b forms nano sheet fins or nano wire fins that are spaced from each other. That is, the nano epitaxy layers 104 a/104 b may be referred as nano sheet or nano wire 104 a/104 b.

Reference is made to FIGS. 12A to 13B. FIG. 13A is a cross-sectional view taken along a cross-sectional line of FIG. 12A. FIG. 13B is a cross-sectional view taken along a cross-sectional line of FIG. 12B. The gate structures 230 are formed respectively in the gate trenches to surround or wrap around the nano sheet fins or nano wire 104 a/104 b simultaneously.

The gate structures 230 include an interfacial layer 236, gate dielectrics 232 formed over the interfacial layer 236, and gate metals 234 formed over the gate dielectrics 232. The gate dielectrics 232, as used and described herein, include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The gate metals 234 may include a metal, metal alloy, and/or metal silicide.

In some embodiments, the gate structures 230 extend in a direction 140 crossing the direction 130 in which the nano sheet fins or nano wire 104 a/104 b extend. The direction 140 may be perpendicular to the direction 130. The gate structures 230 fill into the gate trenches to surround or wrap the nano sheet fins or nano wire 104 a/104 b respectively.

Reference is made to FIGS. 13A to 13B. In some embodiments, a quantity of the nano wires 104 a of each fin structure 105 a is equal to that of the nano wires 104 b of the fin structure 105 b. Each fin structure 105 a includes a base fin 101 a and plural nano wires 104 a located vertically aligned with the base fin 101 a. The nano wires 104 a are spaced from the base fin 101 a and from each other. Each fin structure 105 b includes a base fin 101 b and plural nano wires 104 b located vertically aligned with the base fin 101 a. The nano wires 104 b are spaced from the base fin 101 b and from each other.

In some embodiments, the nano wires 104 a of at least one fin structure 105 a have a uniform thickness (T) that is substantially equal to a uniform thickness (T) of the nano wires 104 b of at least one fin structure 105 b. The thickness (T) of the nano wires 104 a or 104 b is measured in a direction 150 that is perpendicular to the direction 140.

In some embodiments, a uniform pitch (S) between adjacent nano wires 104 a of at least one fin structure 105 a is substantially equal to a uniform pitch (S) between adjacent nano wires 104 b of at least one fin structure 105 b. The uniform pitch (S) of the fin structures 105 a/105 b is measured in a direction 150 that is perpendicular to the direction 140.

In some embodiments, the nano wires 104 a of at least one fin structure 105 a have a uniform width (D1) that is smaller than a uniform width (D2) of the nano wires 104 b of at least one fin structure 105 b. The widths (D1 or D2) of the nano wires 104 a or 104 b are measured in the direction 140.

In some embodiments, the nano wires 104 a of at least one fin structure 105 a have a uniform width (D1) ranging from about 3 nm to about 7 nm. In some embodiments, the nano wires 104 b of at least one fin structure 105 b have a uniform width (D2) ranging from about 8 nm to about 16 nm. In some embodiments, the width (D2) of the nano wire 104 b may be two times greater than the width (D1) of the nano wire 104 a, but may not be greater than three times the width (D1) of the nano wire 104 a because the gate structure may not have enough width to warp around the nano wire 104 b with such width.

In some embodiments, the uniform pitch (S) between adjacent nano wires 104 a or between adjacent nano wires 104 b ranges from about 2 nm to about 10 nm. In some embodiments, the uniform thickness (T) of each nano wire 104 a or each nano wire 104 b ranges from about 3 nm to about 7 nm.

In some embodiments, a quantity of the nano wires 104 a of each fin structure 105 a is from 2 to 10 and a quantity of the nano wires 104 b of each fin structure 105 b is from 2 to 10.

In some embodiments, each nano wire 104 a or 104 a is wrapped by the interfacial layer 236, the gate dielectric 232 and the gate metal 234.

In some embodiments, the gate metals 234 included in the gate structures 230 may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a work function to enhance the device performance (work function metal layer), liner layer, wetting layer, adhesion layer and a conductive layer of metal, metal alloy or metal silicide. For example, the gate metals 234 may be an n-type or p-type work function layer. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer may include a plurality of layers. The work function layer(s) may be deposited by CVD, PVD, electro-plating and/or other suitable process.

In some embodiments, the interfacial layer 236 may include a dielectric material such as silicon oxide (SiO₂), HfSiO, and/or silicon oxynitride (SiON). The interfacial layer 236 may be formed by chemical oxidation, thermal oxidation, ALD, CVD, and/or other suitable method. The gate dielectrics 232 may include a high-K dielectric layer such as hafnium oxide (HfO2). Alternatively, the gate dielectric 212 may include other high-K dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al₂O₃, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable material. The gate dielectrics 232 may be formed by ALD, PVD, CVD, oxidation, and/or other suitable methods.

According to aforementioned embodiments, a semiconductor device includes a first fin structure and a second fin structure located over a substrate. The first fin structure has a single stack of first nano wires or sheets with larger width or diameter and the second fin structure has multiple stacks of second nano wires or sheets with smaller width or diameter for design flexibility. Because the first and second fin structures are concurrently formed, the single stack of first nano wires or sheets and multiple stacks of second nano wires or sheets all have equal sheet numbers and substantially the same pitch and thickness. With such configuration, the single stack of first nano wires or sheets with larger width or diameter may obtain speed gain and the multiple stacks of second nano wires or sheets need smaller width or diameter to aggress fin pitch shrinkage for even scaled down process.

Embodiments for manufacturing semiconductor structures are provided. The method may include forming a first mask structure and a second mask structure over a semiconductor stack, and the second mask structure may have spacers formed on its sidewalls. The semiconductor stack may be patterned through the first mask structure, the second mask structure, and the spacers to form a first fin structure under the first mask structure and the second fin structure under the second mask structure and the spacers. That is, the fin structure with different widths may be formed concurrently and the design flexibility may be increased.

An embodiment of the present disclosure is a semiconductor device having a semiconductor substrate, a first fin structure and a second fin structure. The first fin structure includes a first fin and at least two first nano wires located above the first fin, and the first fin protrudes from the semiconductor substrate. The second fin structure includes a second fin and at least two second nano wires located above the second fin, and the second fin protrudes from the semiconductor substrate. Each first nano wire has a first width different from a second width of each second nano wire.

An embodiment of the present disclosure is that each first nano wire has a first thickness substantially equal to a second thickness of each second nano wire.

An embodiment of the present disclosure is that a quantity of the first nano wires is equal to that of the second nano wires.

An embodiment of the present disclosure is that a first pitch between immediately-adjacent two of the first nano wires is substantially equal to a second pitch between immediately-adjacent two of the second nano wires.

An embodiment of the present disclosure is that the first and second fins and the at least two first and second nano wires are arranged in a first direction, and the first and second widths are measured in a second direction that is perpendicular to the first direction.

An embodiment of the present disclosure is the semiconductor device further including a first gate structure extending in a third direction crossing the first direction and surrounding the at least two first nano wires.

An embodiment of the present disclosure is the semiconductor device further including a second gate structure extending in a third direction crossing the first direction and surrounding the at least two second nano wires.

An embodiment of the present disclosure is the semiconductor device further including a pair of first epitaxy structures, and the at least two first nano wires interconnect the pair of first epitaxy structures.

An embodiment of the present disclosure is the semiconductor device further including a pair of second epitaxy structures, and the at least two second nano wires interconnect the pair of second epitaxy structures.

An embodiment of the present disclosure is that the at least two first nano wires are spaced from the first fin, and the at least two second nano wires are spaced from the second fin.

An embodiment of the present disclosure is a semiconductor device having semiconductor substrate, a first fin structure, a plurality of second fin structures, a first gate structure and a second gate structure. The first fin structure includes a first fin and at least two first nano wires arranged in a first direction, and the first fin protrudes from the semiconductor substrate. Each second fin structure includes a second fin and at least two second nano wires arranged in the first direction, and the second fin protrudes from the semiconductor substrate. The first gate structure extends in a second direction crossing the first direction and surrounding the at least two first nano wires of the first fin structure. The second gate structure extends in the second direction crossing the first direction and surrounding the second nano wires of the second fin structures. Each first nano wire has a first width greater than a second width of each second nano wire.

An embodiment of the present disclosure is that the at least two first nano wires have a uniform first thickness.

An embodiment of the present disclosure is that the at least two second nano wires have a uniform second thickness that is substantially equal to the uniform first thickness.

An embodiment of the present disclosure is that the first and second widths are measured in the second direction.

An embodiment of the present disclosure is that a first pitch between any immediately-adjacent two of the first nano wires is uniform.

An embodiment of the present disclosure is that a second pitch between any immediately-adjacent two of the second nano wires is uniform and is substantially equal to the first pitch.

An embodiment of the present disclosure is that the at least two first nano wires are spaced from each other, and the at least two second nano wires are spaced from each other.

An embodiment of the present disclosure is a method for manufacturing a semiconductor device including epitaxially growing a sacrificial layer over a substrate; epitaxially growing a semiconductor layer over the sacrificial layer; depositing a mask layer over the semiconductor layer; patterning the mask layer to form a first mask structure and a second mask structure over the semiconductor layer; forming a spacer cap layer over the first mask structure and the second mask structure; etching the spacer cap layer over the first mask structure, wherein the etched spacer cap layer remains on a sidewall of the second mask structure; etching the semiconductor layer and the sacrificial layer exposed by the first mask structure, the second mask structure, and the etched spacer cap layer to form a first fin under the first mask structure and a second fin under the second mask structure and the etched spacer cap layer, wherein the second fin is wider than the first fin; etching the sacrificial layer in the first fin and the second fin; and forming a first gate structure wrapping around the semiconductor layer in the first fin and forming a second gate structure wrapping around the semiconductor layer in the second fin.

An embodiment of the present disclosure is the method further including patterning the mask layer is performed such that a third mask structure is formed over the semiconductor layer and adjacent the first mask structure, wherein the first and third mask structures have substantially the same width.

An embodiment of the present disclosure is the method further including forming the first gate structure and forming the second gate structure are performed simultaneously.

In some embodiments, methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first epitaxy layers and second epitaxy layers over a substrate to form a semiconductor stack and forming a first mask structure and a second mask structure over the semiconductor stack. The method further includes forming spacers on sidewalls of the second mask and patterning the semiconductor stack to form a first fin structure covered by the first mask structure and a second fin structure covered by the second mask structure and the spacers. The method further includes removing the first epitaxy layers of the first fin structure to form first nanostructures and removing the first epitaxy layers of the second fin structure to form second nanostructures. In addition, the second nanostructures are wider than the first nanostructures. The method further includes forming a first gate structure around the first nanostructures and forming a second gate structure around the second nanostructures.

In some embodiments, methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first epitaxy layers and second epitaxy layers over a substrate and forming a first mask structure over a first region of the substrate and a second mask structure over a second region of the substrate. The method further includes forming a spacer cap layer covering the first region and the second region of the substrate and removing the spacer cap layer over the first region to expose the first mask structure. The method further includes etching the spacer cap layer over the second region to form spacers on sidewalls of the second mask structure and etching the first epitaxy layers and second epitaxy layers not covered by the first mask, the second mask, and the spacers to form a first fin structure under the first mask and a second fin structure under the second mask and the spacers. The method further includes removing the first epitaxy layers in the first fin structure to form first gaps between the second epitaxy layers in the first fin structure and removing the first epitaxy layers in the second fin structure to form second gaps between the second epitaxy layers in the second fin structure. The method further includes forming a first gate structure in the first gaps to form a first transistor in the first region and forming a second gate structure in the second gaps to form a second transistor in the second region.

In some embodiments, methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first epitaxy layers and second epitaxy layers over a substrate to form a semiconductor stack and forming a first mask structure and a second mask structure over the semiconductor stack. The method further includes forming a first spacer on a first sidewall of the second mask structure and a second spacer on a second sidewall of the second mask structure and patterning the semiconductor stack through the first mask structure to form a first fin structure so that the first fin structure has a first width substantially equal to a width of the first mask structure. The method further includes patterning the semiconductor stack through the second mask structure, the first spacer, and the second spacer to form a second fin structure so that the second fin structure has a second width substantially equal to a sum of widths of the second mask structure, the first spacer, and the second spacer. The method further includes removing the first epitaxy layers of the first fin structure to form first nanostructures and removing the first epitaxy layers of the second fin structure to form second nanostructures and forming a first gate structure wrapping around the first nanostructures. The method further includes forming a second gate structure wrapping around the second nano structures.

FIGS. 14A-1, 14B-1, 14C-1, 14D-1, 14E-1, 14F-1, 14G-1, 14H-1, 14I-1, 14J-1, 14K-1, and 14L-1 are perspective views of a method for manufacturing a first device region 20 in a semiconductor structure 300 at various stages in accordance with some embodiments of the present disclosure. FIGS. 14A-2, 14B-2, 14C-2, 14D-2, 14E-2, 14F-2, 14G-2, 14H-2, 14I-2, 14J-2, 14K-2, and 14L-2 are perspective views of a method for manufacturing a second device region 20′ in the semiconductor structure 300 at various stages in accordance with some embodiments of the present disclosure. The process and materials used in forming the semiconductor structure 300 may be similar to, or the same as, those used in forming the structures shown in FIGS. 1 to 13B, which are described above and therefore not repeated herein. More specifically, similar elements in these figures are designated by the same numerals and can include the same or similar materials, and they can be formed by following the same or similar steps; therefore, such details are omitted in the interest of brevity.

Similar to FIG. 1 , a series of nano epitaxy layers 104 and sacrificial nano epitaxy layers 102 are alternately grown on the substrate 100 to form a semiconductor stack, and the pad oxide layer 106, the pad nitride layer 108, and the mask layer 110 are deposited over the semiconductor stack in both the first device region 20 and the second device region 20′, as shown in FIGS. 14A-1 and 14A-2 in accordance with some embodiments.

In some embodiments, the number of sacrificial nano epitaxy layers 102 is the same as the number of nano epitaxy layers 104. In some embodiments, the number of nano epitaxy layers 104 is in a range from about 2 to about 10. In some embodiments, each of the sacrificial nano epitaxy layers 102 has the same thickness and each of the nano epitaxy layers 104 has the same thickness. In some embodiments, the sacrificial nano epitaxy layers 102 and the nano epitaxy layers 104 have different thicknesses. In some embodiments, each of the sacrificial nano epitaxy layers 102 has a thickness in a range from about 2 nm to about 10 nm. In some embodiments, each of the nano epitaxy layers 104 has a thickness in a range from about 3 nm to about 7 nm.

Next, the pad oxide layer 106, the pad nitride layer 108, and the mask layer 110 are patterned to form a first mask structure 210 a and a second mask structure 210 b in the first device region 20 and a third mask structure 210 c and a fourth mask structure 210 d in the second device region 20′, as shown in FIGS. 14B-1 and 14B-2 in accordance with some embodiments. In some embodiments, the first mask structure 210 a, the second mask structure 210 b, the third mask structure 210 c, and the fourth mask structure 210 d have substantially the same width W. In some embodiments, the width W is in a range from about 3 nm to about 7 nm.

In some embodiments, the distance D₃ between the first mask structure 210 a and the second mask structure 210 b is shorter than the distance D₄ between the third mask structure 210 c and the fourth mask structure 210 d. The distance and the width of the mask structures may affect the performance of the resulting semiconductor structure 300 and the details will be described afterwards.

Next, the spacer cap layer 112 is conformally formed over the first mask structure 210 a, the second mask structure 210 b, the third mask structure 210 c, and the fourth mask structure 210 d and over the top surface of the semiconductor stack in both the first device region 20 and the second device region 20′, as shown in FIGS. 14C-1 and 14C-2 in accordance with some embodiments.

After the spacer cap layer 112 is formed, the photo resist layer 113 is formed over the second device region 20′ as a mask structure, while exposing the first device region 20 in accordance with some embodiments. Next, the spacer cap layer 112 in the first device region 20 that is not covered by the photo resist layer 113 is removed to expose the first mask structure 210 a and the second mask structure 210 b, as shown in FIGS. 14D-1 and 14D-2 in accordance with some embodiments. In some embodiments, the spacer cap layer 112 in the first device region 20 is removed by performing an etching process.

Afterwards, the photo resist layer 113 over the second device region 20′ is removed and the remaining spacer cap layer 112 over the second device region 20′ is etched, so that third spacers 222 c are formed on the sidewalls of the third mask structure 210 c to form a widened third mask structure 210 c′ and fourth spacers 222 d are formed on the sidewalls of the fourth mask structure 210 d to form a widened fourth mask structure 210 d′, as shown in FIGS. 14E-1 and 14E-2 in accordance with some embodiments. In some embodiments, the mask layers 110 are removed.

In some embodiments, the width W₃ of the widened third mask structure 210 c′ (i.e. the sum of the widths of the third mask structure 210 c and the third spacers 222 c) is substantially equal to the width W₄ of the widened fourth mask structure 210 d′ (i.e. the sum of the widths of the fourth mask structure 210 d and the fourth spacers 222 d). In some embodiments, the width W₃ of the widened third mask structure 210 c′ and the width W₄ of the widened fourth mask structure 210 d′ are in a range from about 8 nm to about 16 nm. In some embodiments, the ratio of the width W₃ of the widened third mask structure 210 c′ (or the width W₄ of the widened fourth mask structure 210 d′) to the width W of the first mask structure 210 a (or the width W of the second mask structure 210 b) is in a range from about 1.14 to about 5.3.

In some embodiments, the distance D₃ between the first mask structure 210 a and the second mask structure 210 b is shorter than the distance D₅ between the widened third mask structure 210 c′ and the widened fourth mask structure 210 d′. In some embodiments, the ratio of the distance D₅ to the distance D₃ is in a range from about 1.15 to about 2. As described previously, the distance and the width of the mask structures may affect the performance of the resulting semiconductor structure 300 and the details will be described afterwards.

After the third spacers 222 c and the fourth spacers 222 d are formed, the semiconductor stack and the substrate 100 are patterned using the first mask structure 210 a, the second mask structure 210 b, the widened third mask structure 210 c′, and the widened fourth mask structure 210 d′ to form a first fin structure 205 a, a second fin structure 205 b, a third fin structure 205 c, and a fourth fin structure 205 d respectively, as shown in FIGS. 14E-1 and 14E-2 in accordance with some embodiments.

More specifically, the semiconductor stack and the substrate 100 not covered by the first mask structure 210 a, the second mask structure 210 b, the widened third mask structure 210 c′, and the widened fourth mask structure 210 d′ are etched to form recesses in accordance with some embodiments. As shown in FIG. 14E-1 , the sidewalls of the first mask structure 210 a are substantially aligned with the sidewalls of the first fin structures 205 a, and the sidewalls of the second mask structure 210 b are substantially aligned with the sidewalls of the second fin structures 205 b in accordance with some embodiments. In some embodiments, the first fin structure 210 a and the second fin structure 210 b also have the width W, and the distance between the first fin structure 210 a and the second fin structure 210 b is substantially equal to the distance D₃.

Similarly, the sidewalls of the widened third mask structure 210 c′ are substantially aligned with the sidewalls of the third fin structures 205 c, and the sidewalls of the widened fourth mask structure 210 d′ are substantially aligned with the sidewalls of the fourth fin structures 205 d in accordance with some embodiments. In some embodiments, the third fin structure 210 c and the fourth fin structure 210 d also have the width W₃ and the width W₄ respectively, and the distance between the third fin structure 210 c and the fourth fin structure 210 d is substantially equal to the distance D₄.

Next, the first mask structure 210 a, the second mask structure 210 b, the widened third mask structure 210 c′, and the widened fourth mask structure 210 d′ are removed, and the field oxide layer 114 is formed around the first fin structure 205 a, the second fin structure 205 b, the third fin structure 205 c, and the fourth fin structure 205 d to form a shallow trench isolation (STI), as shown in FIGS. 14F-1 and 14F-2 in accordance with some embodiments.

After the field oxide layer 114 is formed, the thin oxide layer 155 is formed over the field oxide layer 114 and over the first fin structure 205 a, the second fin structure 205 b, the third fin structure 205 c, and the fourth fin structure 205 d in accordance with some embodiments. Afterwards, a dummy gate 280 is formed across the first fin structure 205 a and the second fin structure 205 b and a dummy gate 280′ is formed across the third fin structure 205 c and the fourth fin structure 205 d, as shown in FIGS. 14G-1 and 14G-2 in accordance with some embodiments. In some embodiments, the mask layers 182 and 184 are formed over the dummy gates 280 and 280′. Processes and materials for forming the dummy gates 280 and 280′ may be similar to, or the same as, those for forming the dummy gates 180 a and 180 b described above and are not repeated herein.

Next, the gate spacers 190 are formed on the sidewalls of the dummy gates 280 and 280′, and the oxide layer 155 exposed from the dummy gates 280 and 280′ and the gate spacers 190 are removed, as shown in FIGS. 14H-1 and 14H-2 in accordance with some embodiments. Afterwards, inner spacers and source/drain features are formed in the first fin structure 205 a, the second fin structure 205 b, the third fin structure 205 c, and the fourth fin structure 205 d, as shown in FIGS. 14H-1 and 14H-2 in accordance with some embodiments.

More specifically, the first fin structure 205 a and the second fin structure 205 b not covered by the dummy gates 280 and the spacers 190 are recessed to form first recesses in the first fin structure 205 a and second recesses in the second fin structure 205 b, and the inner spacers (not shown, similar to the inner spacers 192 shown in FIG. 9 ), first source/drain features 200 a, and second source/drain features 200 b are formed in the first recesses and the second recesses in accordance with some embodiments. In addition, the neighboring first source/drain feature 200 a and the second source/drain feature 200 b are merged into a large source/drain feature since the first fin structure 205 a and the second fin structure 205 b are relatively close to each other, as shown in FIG. 14H-1 in accordance with some embodiments.

Similarly, the third fin structure 205 c and the fourth fin structure 205 d not covered by the dummy gates 280′ and the spacers 190 are recessed to form third recesses in the third fin structure 205 c and fourth recesses in the fourth fin structure 205 d, and the inner spacers (not shown, similar to the inner spacers 192 shown in FIG. 9 ), third source/drain features 200 c, and fourth source/drain features 200 d are formed in the third recesses and the fourth recesses in accordance with some embodiments. In addition, the neighboring third source/drain feature 200 c is not in contact with the fourth source/drain feature 200 d since the third fin structure 205 c and the fourth fin structure 205 d are relatively far from each other, as shown in FIG. 14H-2 in accordance with some embodiments. Processes and materials for forming the first, second, third, and fourth source/drain features 200 a, 200 b, 200 c, and 200 d may be similar to, or the same as, those for forming the source/drain features 200 described above and are not repeated herein.

Since the first source/drain feature 200 a and the second source/drain feature 200 b are merged to form a merged source/drain feature, the merged source/drain feature is wider than both the third source/drain feature 200 c and the fourth source/drain feature 200 d, although the third fin structure 205 c and the fourth fin structure 205 d are wider than the first fin structure 205 a and the second fin structure 205 b in accordance with some embodiments. In some embodiments, an air gap is formed between the merged source/drain feature and the isolation feature 114.

After the inner spacers and source/drain features are formed, the etching stop layer 215 and the interlayer dielectric 220 are formed over the first, second, third, and fourth source/drain features 200 a, 200 b, 200 c, and 200 d, as shown in FIGS. 14I-1 and 14I-2 in accordance with some embodiments. A CMP process may be performed to remove the excessive interlayer dielectric 220 and the mask layers 182 and 184.

Next, the dummy gates 280 and 280′ are removed to from gate trenches and the multiple alternatively stacked nano epitaxy layers 104 and sacrificial nano epitaxy layers 102 are exposed, as shown in FIGS. 14I-1 and 14I-2 in accordance with some embodiments. After the dummy gates 280 and 280′ are removed, the sacrificial nano epitaxy layers 102 of the first fin structure 205 a, the second fin structure 205 b, the third fin structure 205 c, and the fourth fin structure 205 d exposed by the gate trenches are removed to form first nanostructures 204 a, second nanostructures 204 b, third nanostructures 204 c, and fourth nanostructures 204 d, as shown in FIGS. 14J-1 and 14J-2 in accordance with some embodiments.

After the first nanostructures 204 a, the second nanostructures 204 b, the third nanostructures 204 c, and the fourth nanostructures 204 d are formed, the gate structure 230 is formed in the first device region 20 and a gate structure 230′ is formed in the second device region 20′, as shown in FIGS. 14K-1 and 14K-2 in accordance with some embodiments. More specifically, the gate structure 230 wraps around the first nanostructures 204 a and the second nanostructures 204 b, and the gate structure 230′ wraps around the third nanostructures 204 c and the fourth nanostructures 204 d in accordance with some embodiments.

FIG. 15-1 illustrates a cross-sectional view of the semiconductor structure 300 taken along a cross-sectional line A-A₁ shown in FIG. 14K-1 in accordance with some embodiments. FIG. 15-2 illustrates a cross-sectional view of the semiconductor structure 300 taken along a cross-sectional line A′-A₁′ shown in FIG. 14K-2 in accordance with some embodiments. FIG. 16-1 illustrates a cross-sectional view of the semiconductor structure 300 taken along a cross-sectional line B-B₁ shown in FIG. 14K-1 in accordance with some embodiments. FIG. 16-2 illustrates a cross-sectional view of the semiconductor structure 300 taken along a cross-sectional line B′-B₁′ shown in FIG. 14K-2 in accordance with some embodiments. FIG. 17-1 illustrates a cross-sectional view of the semiconductor structure 300 taken along a cross-sectional line C-C₁ shown in FIG. 14K-1 in accordance with some embodiments. FIG. 17-2 illustrates a cross-sectional view of the semiconductor structure 300 taken along a cross-sectional line C′-C₁′ shown in FIG. 14K-2 in accordance with some embodiments.

In some embodiments, both the gate structures 230 and 230′ include an interfacial layer 236, gate dielectrics 232 formed over the interfacial layer 236, and gate metals 234 formed over the gate dielectrics 232.

As described above, since the first nanostructures 204 a and the second nanostructures 204 b are patterned through the first mask structure 210 a and the second mask structure 210 b while the third nanostructures 204 c and the fourth nanostructures 204 d are patterned through the widened third mask structure 210 c′ and the widened fourth mask structure 210 d′, the third nanostructures 204 c and the fourth nanostructures 204 d are wider than the first nanostructures 204 a and the second nanostructures 204 b. That is, the effective width of the third nanostructures 204 c and the fourth nanostructures 204 d are greater than that of the first nanostructures 204 a and the second nanostructures 204 b. Accordingly, the device in the second device region 20′ may have a driven current than that in the first device region 20. In some embodiments, the speed of the device in the second device region 20′ is greater (e.g. over 10% higher) than that in the first device region 20.

In some embodiments, the first nanostructures 204 a and the second nanostructures 204 b have the width W in a range from about 3 nm to about 7 nm. In some embodiments, the first nanostructures 204 a and the second nanostructures 204 b has a pitch P₁ in a range from about 20 nm to about 26 nm. The pitch P₁ may be defined as the lateral distance between the lateral center of the first nanostructures 204 a and the lateral center of the second nanostructures 204 b or the lateral distance between the left-most point of the first nanostructures 204 a and the left-most point of the second nanostructures 204 b.

In some embodiments, the third nanostructures 204 c have the width W₃ and the fourth nanostructures 204 d have the width W₄. In some embodiments, the width W₃ is substantially equal to the width W₄ and is in a range from about 8 nm to about 16 nm. In some embodiments, the ratio of the width W₃ to the width W is in a range from about 1.14 to about 2.3.

In some embodiments, the third nanostructures 204 c and the fourth nanostructures 204 d have a pitch P₂ in a range from about 30 nm to about 40 nm. The pitch P₂ may be defined as the lateral distance between the lateral center of the third nanostructures 204 c and the lateral center of the fourth nanostructures 204 d or the lateral distance between the left-most point of the third nanostructures 204 c and the left-most point of the fourth nanostructures 204 d.

Meanwhile, since the first nanostructures 204 a, the second nanostructures 204 b, the third nanostructures 204 c, and the fourth nanostructures 204 d are all patterned from the semiconductor stack of the epitaxy layers 102 and 104, each of the first nanostructures 204 a, the second nanostructures 204 b, the third nanostructures 204 c, and the fourth nanostructures 204 d are aligned with one another in accordance with some embodiments. In addition, all the first nanostructures 204 a, the second nanostructures 204 b, the third nanostructures 204 c, and the fourth nanostructures 204 d have substantially the same thickness in a range from about 3 nm to about 7 nm in accordance with some embodiments. In some embodiments, the first nanostructures 204 a, the second nanostructures 204 b, the third nanostructures 204 c, and the fourth nanostructures 204 d have substantially the same vertical spacing in a range from about 2 nm to about 10 nm

The distance between the first nanostructures 204 a and the second nanostructures 204 b is substantially equal to the distance D₃ between the first fin structure 205 a and the second fin structure 205 b, and the distance between the third nanostructures 204 c and the fourth nanostructures 204 d is substantially equal to the distance D₅ between the third fin structure 205 c and the fourth fin structure 205 d in accordance with some embodiments. The distance described above may be defined as the lateral distance between two nanostructures at the same height or the closest distance between the two sets of nanostructures. In some embodiments, the ratio of the distance D₅ to the distance D₃ is in a range from about 1.15 to about 2.

In some embodiments, the isolation feature 114 formed around the first fin structure 205 a, the second fin structure 205 b, the third fin structure 205 c, and the fourth fin structure 205 d has a curved top surface, as shown in FIGS. 15-1, 15-2, 16-1, 16-2 (the perspective views have been simplified and therefore the curved top surface is not shown in FIGS. 14A-1 to 14K-2 ). In some embodiments, the gate structure 230 has a first curved bottom surface between the first fin structure 205 a and the second fin structure 205 b, and the gate structure 230′ has a second curved bottom surface between the third fin structure 205 c and the fourth fin structure 205 d. In addition, the lowest portion of the first curved bottom surface of the gate structure 230 is higher than the lowest portion of the second curved bottom surface of the gate structure 230′ in accordance with some embodiments.

Although two fin structures and one gate structure are shown in each of the first device region 20 and the second device region 20′, they are only examples and the numbers of the fin structures and the gate structures are not intended to be limiting. For example, a semiconductor wafer may include a number of device regions including fin structures having various widths arranged in different pitches.

FIG. 18-1 illustrates a layout including the first device region 20 of the semiconductor structures 300 and FIG. 18-2 illustrates a layout including the second device region 20′ of the semiconductor structures 300 in accordance with some embodiments.

As shown in FIG. 18-1 , the gate structures 230 are formed across the first fin structure 205 a and the second fin structure 205 c and conductive structures 400 and 410 are formed over the gate structures 230 in accordance with some embodiments. Similarly, the gate structures 230′ are formed across the third fin structure 205 c and the fourth fin structure 205 d and conductive structures 400′ and 410′ are formed over the gate structures 230′, as shown in FIG. 18-2 in accordance with some embodiments.

In some embodiments, the conductive features 400, 410, 400′, and 410′ are made of conductive materials such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other applicable conductive materials, or a combination thereof.

In addition, the conductive features 400, 410, 400′, and 410′ may include a liner and/or a barrier layer. The liner may be made of silicon nitride, although any other applicable dielectric may be used as an alternative. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other applicable processes, such as physical vapor deposition or a thermal process, may be used as an alternative. The barrier layer (not shown) may be formed over the liner (if present) and may cover the sidewalls and bottom of the opening. The barrier layer may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition processes. The barrier layer may be made of tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, may also be used.

As described above, the width W₃ of the third fin structure 205 c and the width W₄ of the fourth fin structure 205 d may be greater than the width W₁ of the first fin structure 205 a and the width W₂ of the second fin structure 205 b. In addition, the pitch P₁ may be smaller than the pitch P₂. The device shown in FIG. 18-2 may provide higher driven current due to greater effective channel widths and therefore may be used in application requiring higher speed and/or performed such as High Performance Computing devices. On the other hand, the device shown in FIG. 18-1 may have better density and may be used in mobile devices. That is, devices with different characters may be manufactured over the same wafer without using complicated processes.

As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value. For example, two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ±10% of an average of the values.

Embodiments of a semiconductor structure and a method for forming the same may be provided. The semiconductor structure may include first nanostructures, second nanostructures, third nanostructures, and fourth nanostructures. In addition, a first gate structure may be formed surrounding the first nanostructures and the second nanostructures, and a second gate structure may be formed surrounding the third nanostructures and the fourth nanostructures. The first nanostructures and the second nanostructures may be narrower than the third nanostructures and the fourth nanostructures and the pitch between the first nanostructures and the second nanostructures may be smaller than the pitch between the third nanostructures and the fourth nanostructures. The device with wider nanostructures and wider widths may have improved performance and speed, while device with narrower nanostructures and narrower widths may have improved device density.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes first silicon-containing layers, second silicon-containing layers, third silicon-containing layers, and fourth silicon-containing layers vertically suspended over a substrate and laterally spaced apart from each other. In addition, the first silicon-containing layers and the second silicon-containing layers are narrower than the third silicon-containing layers and the fourth silicon-containing layers. The semiconductor structure further includes first source/drain features, second source/drain features, third source/drain features, and fourth source/drain features attaching to opposite sides of the first silicon-containing layers, the second silicon-containing layers, the third silicon-containing layers, and the fourth silicon-containing layers, respectively. In addition, the first source/drain features are merged with the second source/drain features while the third source/drain features are spaced apart from the fourth source/drain features.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first device region formed over a substrate. In addition, the first device region includes first silicon-containing layers stacked and spaced apart from each other in a first direction and second silicon-containing layers stacked and spaced apart from each other in the first direction and spaced apart from the first silicon-containing layers in a second direction different from the first direction. the first device region further includes a first gate structure wrapping around the first silicon-containing layers and the second silicon-containing layers, and the first gate structure has a first curved bottom surface between the first silicon-containing layers and the second silicon-containing layers. The semiconductor structure includes a second device region formed over the substrate. In addition, the second device region includes third silicon-containing layers stacked and spaced apart from each other in the first direction and fourth silicon-containing layers stacked and spaced apart from each other in the first direction and spaced apart from the third silicon-containing layers in the second direction. The second device region further includes a second gate structure wrapping around the third silicon-containing layers and the fourth silicon-containing layers, and the second gate structure has a second curved bottom surface between the third silicon-containing layers and the fourth silicon-containing layers. In addition, a lowest portion of the first curved bottom surface of the first gate structure is higher than a lowest portion of the second curved bottom surface of the second gate structure.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes first silicon-containing layers and second silicon-containing layers extending lengthwise in a first direction over a substrate and a first gate structure extending lengthwise in a second direction different from the first direction and wrapping around the first silicon-containing layers and the second silicon-containing layers. The semiconductor structure further includes third silicon-containing layers and fourth silicon-containing layers extending lengthwise in the first direction over the substrate, and the first silicon-containing layers are narrower than the third silicon-containing layers in the second direction. The semiconductor structure further includes a second gate structure extending lengthwise in the second direction and wrapping around the third silicon-containing layers and the fourth silicon-containing layers. In addition, a first distance between the first silicon-containing layers and the second silicon-containing layers in the second direction is smaller than a second distance between the third silicon-containing layers and the fourth silicon-containing layers in the second direction.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure formed over a substrate. The semiconductor structure further includes first nanostructures formed over the first fin structure, second nanostructures formed over the second fin structure, third nanostructures formed over the third fin structure, and fourth nanostructures formed over the fourth fin structure. The semiconductor structure further includes a first gate structure wrapping around the first nanostructures and the second nanostructures, and a second gate structure wrapping around the third nanostructures and the fourth nanostructures. In addition, a first lateral distance between the first fin structure and the second fin structure is smaller than a second lateral distance between the third fin structure and the fourth fin structure, and the first fin structure and the second fin structure are narrower than the third fin structure and the fourth fin structure.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first device region formed over a substrate. The first device region includes first nanostructures and second nanostructures formed over the substrate and a first gate structure wrapping around the first nanostructures and the second nanostructures. The semiconductor structure further includes a second device region formed over the substrate. The second device region includes third nanostructures and fourth nanostructures formed over the substrate. In addition, the third nanostructures are wider than the first nanostructures, and the fourth nanostructures are wider than the second nanostructures. The second device region further includes a second gate structure wrapping around the third nanostructures and the fourth nanostructures. In addition, a closest distance between one of the first nanostructures and one of the second nanostructures is smaller than a closest distance between one of the third nanostructures and one of the fourth nanostructures.

A method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes alternately stacking first epitaxy layers and second epitaxy layers to form a semiconductor stack over a substrate and forming a first mask structure, a second mask structure, a third mask structure, and a fourth mask structure over the semiconductor stack. The method for manufacturing a semiconductor structure further includes forming third spacers on sidewalls of the third mask structure to form a widened third mask structure and fourth spacers on sidewalls of the fourth mask structure to form a widened fourth mask structure and patterning the semiconductor stack through the first mask structure, the second mask structure, the widened third mask structure, and the widened fourth mask structure to form a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure respectively. The method for manufacturing a semiconductor structure further includes removing the first epitaxy layers of the first fin structure, the second fin structure, the third fin structure, and the fourth fin structure to form first nanostructures, second nanostructures, third nanostructure, and fourth nanostructure respectively. In addition, a distance between the first mask structure and the second mask structure is smaller than a distance between the third mask structure and the fourth mask structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A semiconductor structure, comprising: first silicon-containing layers, second silicon-containing layers, third silicon-containing layers, and fourth silicon-containing layers vertically suspended over a substrate and laterally spaced apart from each other, wherein the first silicon-containing layers and the second silicon-containing layers are narrower than the third silicon-containing layers and the fourth silicon-containing layers; first source/drain features, second source/drain features, third source/drain features, and fourth source/drain features attaching to opposite sides of the first silicon-containing layers, the second silicon-containing layers, the third silicon-containing layers, and the fourth silicon-containing layers, respectively, wherein the first source/drain features are merged with the second source/drain features while the third source/drain features are spaced apart from the fourth source/drain features.
 2. The semiconductor structure as claimed in claim 1, further comprising: a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure vertically overlapping the first silicon-containing layers, the second silicon-containing layers, the third silicon-containing layers, and the fourth silicon-containing layers, respectively; a first isolation structure laterally sandwiched between the first fin structure and the second fin structure; a first gate structure wrapping around the first silicon-containing layers and the second silicon-containing layers and extending over the first isolation structure; a second isolation structure laterally sandwiched between the third fin structure and the fourth fin structure; and a second gate structure wrapping around the third silicon-containing layers and the fourth silicon-containing layers and extending over the second isolation structure.
 3. The semiconductor structure as claimed in claim 2, wherein a lateral distance between a first sidewall of the first fin structure and a second sidewall of the second fin structure facing the first sidewall is smaller than a lateral distance between a third sidewall of the third fin structure and a fourth sidewall of the fourth fin structure facing the third sidewall.
 4. The semiconductor structure as claimed in claim 3, wherein an interface between the second gate structure and the third fin is lower than a tip portion of the second isolation structure over the third sidewall of the third fin structure.
 5. The semiconductor structure as claimed in claim 2, wherein the second gate structure comprises an interfacial layer, a gate dielectric layer, and a gate metal layer, and the gate dielectric layer and the second isolation structure has a curved interface.
 6. The semiconductor structure as claimed in claim 5, wherein a middle region of the curved interface between the gate dielectric layer and the second isolation structure is lower than an interface between the interfacial layer and the gate dielectric layer vertically under the third silicon-containing layers.
 7. A semiconductor structure, comprising: a first device region formed over a substrate, wherein the first device region comprises: first silicon-containing layers stacked and spaced apart from each other in a first direction; second silicon-containing layers stacked and spaced apart from each other in the first direction and spaced apart from the first silicon-containing layers in a second direction different from the first direction; and a first gate structure wrapping around the first silicon-containing layers and the second silicon-containing layers, wherein the first gate structure has a first curved bottom surface between the first silicon-containing layers and the second silicon-containing layers; and a second device region formed over the substrate, wherein the second device region comprises: third silicon-containing layers stacked and spaced apart from each other in the first direction; fourth silicon-containing layers stacked and spaced apart from each other in the first direction and spaced apart from the third silicon-containing layers in the second direction; and a second gate structure wrapping around the third silicon-containing layers and the fourth silicon-containing layers, wherein the second gate structure has a second curved bottom surface between the third silicon-containing layers and the fourth silicon-containing layers, wherein a lowest portion of the first curved bottom surface of the first gate structure is higher than a lowest portion of the second curved bottom surface of the second gate structure.
 8. The semiconductor structure as claimed in claim 7, wherein the second gate structure has a first portion overlapping the third silicon-containing layers in the first direction and a second portion between the third silicon-containing layers and the fourth silicon-containing layers, and a bottom surface of the first portion is higher than a bottom surface of the second portion.
 9. The semiconductor structure as claimed in claim 7, further comprising: a first source/drain feature physically attaching to both the first silicon-containing layers and the second silicon-containing layers; a third source/drain feature physically attaching to the third silicon-containing layers; and a fourth source/drain feature physically attaching to the fourth silicon-containing layers, wherein the first source/drain feature is wider than both the third source/drain feature and the fourth source/drain feature in the second direction.
 10. The semiconductor structure as claimed in claim 9, wherein the third source/drain feature is spaced apart from the fourth source/drain feature.
 11. The semiconductor structure as claimed in claim 9, wherein the first source/drain feature has a first portion attaching to the first silicon-containing layers, a second portion attaching to the second silicon-containing layers, and a third portion between the first portion and the second portion, and a top surface of the third portion is lower than a top surface of the first portion and a top surface of the second portion.
 12. The semiconductor structure as claimed in claim 7, wherein the third silicon-containing layers and the fourth silicon-containing layers are wider than the first silicon-containing layers and the second silicon-containing layers in the second direction.
 13. The semiconductor structure as claimed in claim 12, wherein each of the first silicon-containing layers, the second silicon-containing layers, the third silicon-containing layers, and the fourth silicon-containing layers are substantially aligned with each other in the second direction.
 14. A semiconductor structure, comprising: first silicon-containing layers and second silicon-containing layers extending lengthwise in a first direction over a substrate; a first gate structure extending lengthwise in a second direction different from the first direction and wrapping around the first silicon-containing layers and the second silicon-containing layers; third silicon-containing layers and fourth silicon-containing layers extending lengthwise in the first direction over the substrate, wherein the first silicon-containing layers are narrower than the third silicon-containing layers in the second direction; and a second gate structure extending lengthwise in the second direction and wrapping around the third silicon-containing layers and the fourth silicon-containing layers, wherein a first distance between the first silicon-containing layers and the second silicon-containing layers in the second direction is smaller than a second distance between the third silicon-containing layers and the fourth silicon-containing layers in the second direction.
 15. The semiconductor structure as claimed in claim 14, wherein the first silicon-containing layers, the second silicon-containing layer, the third silicon-containing layers, and the fourth silicon-containing layers have substantially a same thickness in a third direction substantially perpendicular to the first direction and the second direction.
 16. The semiconductor structure as claimed in claim 14, further comprising: a first fin structure protruding from the substrate and below the first silicon-containing layer; a second fin structure protruding from the substrate and below the second silicon-containing layer; a third fin structure protruding from the substrate and below the third silicon-containing layer; and a fourth fin structure protruding from the substrate and below the first silicon-containing layer.
 17. The semiconductor structure as claimed in claim 16, further comprising: a first isolation structure formed around the first fin structure and the second fin structure over the substrate; and a second isolation structure formed around the third fin structure and the fourth fin structure over the substrate, wherein the first isolation structure has a first curved top surface between the first fin structure and the second fin structure, and the second isolation structure has a second curved top surface between the third fin structure and the fourth fin structure, and a lowest portion of the first curved top surface is higher than a lowest portion of the second curved top surface.
 18. The semiconductor structure as claimed in claim 14, wherein a ratio of the second distance to the first distance is in a range from about 1.15 to about
 2. 19. The semiconductor structure as claimed in claim 14, wherein the first silicon-containing layers and the second silicon-containing have substantially a same first width, and the third silicon-containing layers and the fourth silicon-containing have substantially a same second width.
 20. The semiconductor structure as claimed in claim 14, further comprising: a first isolation structure formed between the first silicon-containing layers and the second silicon-containing layers; and a second isolation structure formed between the third silicon-containing layers and the fourth silicon-containing layers, wherein a lowest portion of a top surface of the first isolation structure is higher than a lowest portion of a second top surface of the second isolation structure. 